Simulator Arsitektural Dari Sirkuit Elektronis Guna Tujuan Pembelajaran

Suryo Bramasto
Sunarto Sunarto


The electronic circuit engineering learning processes generally requires specific infrastructures which sometimes constrained to cost factors in the procurement. Circuit simulator could be an alternative as electronic circuit engineering learning tool. Architectural simulation provides designers the ability to quickly examine a wide variety of design choices. The recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, a simulator that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency, energy, power brightness, or current draw) on a cycle-by-cycle basis is presented. As for learning purpose, circuit template and pre-built circuits for many categories are provided. The environment enables process visualization and simulation of analog and digital circuits. The system enables the creation of many laboratory exercises, which offer students opportunities to follow visually characteristic processes in analog and digital circuits. At this research, Rational Unified Process (RUP) software process model and Object Oriented Programming (OOP) are implemented.
Keywords: architectural simulation, circuit simulation, learning, RUP, OOP

Full Text:



Austin, T., Larson, E., dan Ernst, D., Februrari 2002. Simplescalar: An infrastructure for computer system modeling. IEEE Computer.

Cai, G., Seng, John S., dan Tullsen, Dean M., 30 September – 3 Oktober 2012. Retrospective on “Power-Sensitive Multi Threaded Architecture”. In 2012 IEEE 30th International Conference on Computer Design (ICCD).

Calder, B., 2003. Simpoint, [online] Tersedia di: [Diakses 28 Juni 2018]

Ernst, D., Kim, N.S., Das, S., Pant, S., Pham, T., Rao, R., Ziesler, C., Blaauw, D., Austin, T., Mudge, T., dan Flautner, K., Desember 2003. Razor: A low-power pipeline based on circuit-level timing speculation. 36th Annual International Symposium on Microarchitecture (MICRO-36).

Falstad, Paul., 2015. Circuit Simulator Applet, [online] Tersedia di: [Diakses 9 Juni 2018]

Ghiasi, S. dan Grunwald, D., Desember 2000. A comparison of two architectural power models. Workshop on Power Aware Computing Systems (PACS-2000).

Jacobson, Sten., 2002. The Rational Objectory Process–A UML Based Software Engineering Process, [online] Tersedia di: [Diakses 18 Juni 2018]

Lipasti, M.H. dan Ravi, G.S., 24 – 28 Juni 2017. CHARSTAR: Clock hierarchy aware resource scaling in tiled architecture. 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

Sherwood, T., McMahan, J., Cui, W., Xia, L., Heckey, J., dan Chong, Frederic T., 1 – Mei 2017. Challenging on-chip SRAM security with boot-state statistics. 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Sherwood, T., Kastner, R., dan Oberg, J., 2013. Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip. IEEE Design & Test – Volume: 30, Issue: 2 – 2013 – pages: 55-62.

Kevin Skadron, Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Mircea R. Stan, 5 – 8 November 2017. Pre-RTL Voltage and Power Optimization for Low Cost, Thermally Challenged Multicore Chips. 2017 IEEE International Conference on Computer Design (ICCD).

Weaver, C. dan Austin, T., Juni 2001. A fault tolerant approach to microprocessor design. IEEE International Conference on Dependable Systems and Networks (DSN-2001).


Article metrics

Abstract views : 48 | Full Text views : 46


Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.


DOAJ faktor exacta Garuda Ristekdikti isjd sinta isjd pkp index

isjd Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

Flag Counter

stats View Faktor Exacta Stats

pkp index